There is great interest and demand to adopt Complementary Metal-Oxide Semiconductor (CMOS) Commercial-Off-The-Shelf (COTS) Integrated Circuits (ICs) instead of space-grade ICs in space applications, largely due to their higher performance (including functionalities), lower cost and availability. It is also well-known that COTS ICs are subjective to various radiation effects including the accumulative effect of Total Ionizing Dose (TID) and a number of single-event effects such as those described as Single Event Transient (SET), Single Event Upset (SEU) and Single Event Latch-up (SEL), etc. Amongst said radiation effects, SEL is the most devastating because, unlike other effects that largely introduce errors or degrade performance, SEL may permanently destroy COTS ICs.
SEL occurs when a parasitic Silicon Controlled Rectifier structure in a CMOS IC is activated by energetic particles such as heavy ions, protons or neutrons, and this induces a huge current. The consequences of SEL include soft failures such as loss of data or logic state, and destructive hard failures if ICs are subject to SEL current for an excessive period of time.
In view of this, there is a real need for an SEL detection and protection circuit for COTS ICs in space applications.
FIG. 1 depicts a block diagram of a conventional SEL detection and protection circuit 10. The SEL detection and protection circuit 10 serves to shut down (i.e. disable the power to) a target COTS IC 12 when SEL occurs, and restarts (i.e. reconnects) a power supply via a power switch 14 to the target IC 12 when the SEL effect is removed.
In the conventional approach, the SEL detection and protection circuit 10 is realised by an over-current protection circuit 16 as depicted in FIG. 1. The over-current protection circuit 16 senses the load current I of the target IC 12 via a current sensor 18 and compares it against a pre-determined threshold current ith. When SEL happens, the load current I exceeds the threshold current ith, and the over-current protection circuit 16 is triggered to shut down the target IC 12 by means of disconnecting the power via switch 14.
Although the conventional SEL protection approach can theoretically protect target ICs from large SEL currents, there are some shortcomings in practical space applications. Firstly, it is very challenging to determine an appropriate threshold current. Specifically, the load current of target ICs can be in a large range, depending on the specific ICs, and the load current may further deviate substantially from its nominal range due to radiation effects, temperature variations, aging, etc. Hence, to avoid false triggering, the threshold current is usually set much higher than the nominal current (e.g. 4-5 times), and consequently, the target ICs may inadvertently be subjected to a large SEL current for an extended period before the protection is triggered. Secondly, it is well-known that micro latch-up may occur in some COTS ICs (depending on the fabrication process, layout, etc.). The conventional approach, that requires a high threshold current, may not be effective to detect such micro latch-up that usually dissipates at a localised low current. Nevertheless, micro latch-up may result in localised damage. In short, the conventional approach to SEL detection and protection is inadequate.
It is therefore an aim of the present invention to provide an improved electronic circuit for single-event latch-up (SEL) detection and protection that is particularly well suited to space applications.